1. Field of the Invention
The present invention relates to a data readout circuit, a data readout method, and a data storage device.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing the structure of a conventional ferroelectric memory. As shown in FIG. 1, the conventional ferroelectric memory comprises a word line WL, a bit line BL, a ferroelectric capacitor CF, n-channel MOS transistors 12, 14, 17A, 17B, 18A, 18B, and Ti, p-channel MOS transistors T8 to T10, capacitors 19 and 22, and nodes NA and NB. The bit line BL has a bit line stray capacitance CBL.
Here, the gate of the n-channel MOS transistor 14 is connected to the word line WL. One terminal of the source/drain of the n-channel MOS transistor 14 is connected to the bit line BL, while the other terminal is connected to the ferroelectric capacitor CF. A plate line CP is connected to one terminal of the ferroelectric capacitor CF.
A voltage VCON is supplied to the n-channel MOS transistors 17A and 17B, while a reference voltage Vref is supplied to the source/drain of the n-channel MOS transistor 17A. A voltage VN is supplied to the gate of the n-channel MOS transistor 12, and a voltage RES is supplied to the gate of the n-channel MOS transistor T1. A voltage VP is supplied to the gate of the p-channel MOS transistor T8.
In the above ferroelectric memory, the single n-channel MOS transistor 14 and the single ferroelectric capacitor CF constitute one ferroelectric memory cell, as shown in FIG. 1. This ferroelectric capacitor CF holds digital information consisting of 1 or 0 in a non-volatile state by taking a reverse polarized state.
Next, an operation to write the data in the ferroelectric memory cell will be described. When the information of xe2x80x9c1xe2x80x9d is written in the ferroelectric memory cell, the potential of the bit line BL serves as a ground potential. When the information of xe2x80x9c0xe2x80x9d is written in the ferroelectric memory cell, the potential of the bit line BL serves as a power potential Vcc. The word line WL is then activated, so that the n-channel MOS transistor 14 is energized and that the potential of the plate line CP changes from the ground potential to the power source potential Vcc and returns to the ground potential. Receiving the voltage, the ferroelectric capacitor CF shifts to a predetermined polarized state, and holds the information of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. When the data write operation is completed, the potential of the bit line BL is returned to the ground potential.
Next, an operation to read out data from the ferroelectric memory cell will be described. In this case, the potential of the bit line BL serves as the ground potential. The word line WL is activated, so that the n-channel MOS transistor 14 is energized, and that the potential of the plate line CP shifts from the ground potential to the power source potential Vcc, thereby moving the charges polarized to the ferroelectric capacitor CF to the bit line BL. Here, the potential of the bit line BL greatly or slightly rises depending on the polarized state of the ferroelectric capacitor CF.
For instance, a latched sense amplifier circuit compares the potential of the bit line BL with the reference potential. In the initial state, the power source to the sense amplifier circuit is off, and when voltage is applied to the two input terminals, the power is supplied to the sense amplifier circuit. At this point, the input terminal having the potential higher than the other rises to the power source potential Vcc, and the input terminal having the potential lower than the other drops to the ground potential. By this sense amplifier circuit, data held by the ferroelectric capacitor CF can be read out.
FIGS. 2A to 2I are timing charts showing the data read-out operation performed by the conventional ferroelectric memory shown in FIG. 1. As shown in FIGS. 2A and 2B, a voltage VCON and a signal RES are activated from 0 V (low level) to 3 V (high level) at time t1. By doing so, the potential of the bit line BL is initialized to 0 V, as shown in FIG. 2G. As shown in FIG. 2A, the voltage VCON is high until time t4.
As shown in FIG. 2C, the word line WL is activated at time t2, and the n-channel MOS transistor 14 is switched on. As shown in FIG. 2D, the potential of the plate line CP rises from 0 V to the power source potential (3 V) at time t3. Here, the potential of the bit line BL rises depending on the polarized charge amount of the ferroelectric capacitor CF, as shown in FIG. 2G.
In FIGS. 2G to 2I, each converted capacitance value, 0.2 pF, of the ferroelectric capacitor CF is indicated by a solid line, while each converted capacitance value, 0.05 pF, is indicated by a broken line. As can be seen from the timing charts, the larger the polarized charge amount, the higher the potential of the bit line BL. When the converted capacitance value of the ferroelectric capacitor CF is 0.2 pF, the potential of the bit line BL rises up to 0.5 V, which will be described more later.
Next, as shown in FIG. 2E, the voltage VN to be supplied to the gate of the n-channel MOS transistor 12 that serves as a power switch for a sense amplifier is shifted to the high level at time t5. Here, as shown in FIGS. 2H and 2I, if the potential of the node NA (the potential of the bit line BL) is lower than the potential of the node NB (the reference voltage Vref), the potential of the node NA becomes 0 V while the potential of the node NB becomes equal to the reference voltage Vref, as indicated by the broken lines. On the other hand, the potential of the node NA is higher than the potential of the node NB, the potential of the node NA does not fluctuate, but the potential of the node NB shifts to 0 V, as indicated by the solid lines.
Next, as shown in FIG. 2F, a voltage VP to be supplied to the gate of the p-channel MOS transistor T8 that serves as a VCC power switch for a sense amplifier is shifted to the low level at time t6. As shown in FIGS. 2H and 2I, if the potential of the node NA is lower than the potential of the node NB, the potential of the node NA is 0 V while the potential of the node NB becomes 3 V, as indicated by the broken lines. On the other hand, if the potential of the node NA is higher than the potential of the mode NB, the potential of the node NA becomes 3V while the potential of the node NB remains 0 V, as indicated by the solid lines.
As described above, after one of the potentials of the node NA and the node NB is shifted to 0 V while the other one of the potentials is shifted to 3 V, the potential of the node NA is transmitted via the bit line BL, so that the information stored in the ferroelectric memory cell is read out.
In the process of reading out information from the conventional ferroelectric memory shown in FIG. 1, the potential of the bit line rises depending on the polarization of the ferroelectric capacitor. Assuming that a cell capacitance value determined from the polarized charge amount of the ferroelectric capacitor and the voltage supplied between the electrodes is about 0.2 pF, the parasitic capacitance of the bit line is 1 pF, and the power source voltage is 3 V, the voltage of the bit line rises, by 0.5 V, which is calculated by 3 Vxc3x970.2 pF/(0.2 pF +1pF), when the plate line rises from 0 V to 3 V. The potential of the bit line is shown in FIG. 2G. Accordingly, the voltage to be supplied to the ferroelectric capacitor becomes 2.5 V, which is calculated by 3 Vxe2x88x920.5 V.
Intensive studies have been made on lowering the read-out voltage of the properties of the ferroelectric capacitor. However, polarized electric charge cannot adequately read out with a low read-out voltage, which results in inaccurate information read-out and reduction of read-out margins.
Meanwhile, to reduce the power consumption of portable telephones and mobile electronic equipment, there has been a strong demand for lowering the power source voltage as well. If the bit line capacitance is increased, a rise of the voltage of the bit line can be reduced and a larger voltage difference can be applied across a ferroelectric capacitor. However, a read-out signal becomes smaller at the same time. As a result, in a latch-type sense amplifier circuit in a ferroelectric memory, a wrong operation is often caused due to an error in the input offset voltage.
Therefore, it is necessary to design the latch-type sense amplifier circuit, so that a rise of the voltage of the bit line can be restricted to about 0.5 V. However, when the power source voltage drops to 2 V or 1 V, it is difficult to supply sufficient voltage across the ferroelectric capacitor.
A general object of the present invention is to provide data storage devices in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a data storage device that has high reliability and less power consumption, and a data read-out circuit and a data read-out method employed in the data storage device.
The above objects of the present invention are achieved by a data storage device that comprises: a memory cell connected between a plate line and a bit line; and a potential holding unit that maintains a potential of the bit line at a predetermined potential so as to prevent a fluctuation of the potential of the bit line even when a voltage is supplied to the plate line.
With this data storage device, the electric charge accumulated in the memory cell can be read out without fail.
The above objects of the present invention are also achieved by a data read-out circuit that reads out data from a memory cell, comprising: a charge accumulating unit that accumulates electric charge supplied; a charge transfer unit that transfers the electric charge accumulated in the memory cell to the charge accumulating unit in accordance with the data; and an amplifier unit that amplifies a voltage generated by the electric charge accumulated in the charge accumulating unit, and reads out the data from the memory cell.
The above objects of the present invention are also achieved by a data storage device that comprises: a bit line; a memory cell that is connected to the bit line; a charge accumulating unit that accumulates electric charge supplied; a charge transfer unit that transfers electric charge to the charge accumulating unit, the electric charge being accumulated in the memory cell based on stored data and then outputted onto the bit line at the time of reading out the data; and an amplifier unit that amplifies a voltage generated by the electric charge accumulated in the charge accumulating unit, and reads out data from th e memory cell.
With this data storage device, data can be read out without fail, in accordance with the electric charge accumulated in the memory cell and outputted onto the bit line.
The above objects of the present invention are also achieved by a method of reading out data from a memory cell, comprising the steps of: transferring electric charge accumulated in the memory cell to a charge accumulating unit in accordance with the data; and amplifying a voltage generated by the electric charge accumulated in the charge accumulating unit, so as to reading the data from the memory cell.
The above and other objects and features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.